1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly to selection circuits of spare memory cells, in which defective memory cells are replaced by spare memory cells to substantially remove defects from the semiconductor memory device.
2. Description of the Related Art
FIG. 1 shows a block diagram of a dynamic random access memory (DRAM) 100, in which a memory word having a defective memory cell is replaced by a spare memory word to substantially eliminate defective cells from a semiconductor memory device. The DRAM 100 mainly has a primary memory cell array 112, a redundant memory cell array 113, a data bus 114, an input/output circuit 115 and a word selection circuit 130. The word selection circuit 130 mainly includes an input buffer block 101 that receives an address signal 120, an input buffer block 102 that receives a command signal 121, a command decoder 103, a RAS (Row Address Strobe) main signal generation circuit 104, an address latch circuit 105, an address amplifier block 106, a pre-decode circuit 107, a primary word decoder 108, a row redundant address decision circuit 109, a redundant word decoder 110 and a word decoder trigger signal generation circuit 111. FIG. 2 shows a flow chart of selection of primary word lines of the primary memory cell array 112 and selection of redundant word lines for the redundant memory cell array 113 when an address signal 120 is supplied to the DRAM 100. First, the selection of both word lines as shown in FIG. 2 will be explained.
In FIG. 2, the address signal is supplied to the DRAM 100 as shown in FIG. 1 in a step S1. The supplied address signal is latched in a step S2 and amplified. Next, in the step S3, a row redundancy decision is made with regard to the amplified address signal. If the supplied address corresponds to the row address which selects the word line of the memory word including the defective memory cells, it is decided that the row redundancy operation is performed. Then, in the step S4, the redundant word decoder 110 as shown in FIG. 1 is selected. Then, the redundant word decoder 110 as shown in FIG. 1 is activated in a step S5 and the redundant word line RWL as shown in FIG. 1 is activated. On the other hand, if the supplied address does not correspond to the row address which selects the word line of a memory word that includes a defective memory cell, the row redundancy operation will not be made. Then, in the step S6, the primary word decoder 108 as shown in FIG. 1 is selected and in a step S7 the primary word line WL is activated.
Next, an operation of the DRAM 100 will be explained using FIG. 1. First, the address signal 120 is supplied to the input buffer 101. The address signal 120 is latched synchronously with an internal clock by the input buffer 101 and the address latch circuit 105, then the latched address signal is supplied to the address amplifier block 106. On the other hand, the command signal 121 is also supplied to the input buffer 102. Then, the command signal 121 is latched synchronously with the internal clock by the input buffer 102 and is supplied to the command decoder 103. The command decoder decodes the command and generates various signals needed for following circuit operations. Some of output signals from the command decoder 103 are supplied to the RAS main signal generation circuit 104. The RAS main signal generation circuit 104 generates various main signals needed for the row address circuits, such as the row redundant address decision circuit 109, to operate. The address latch signal needed for the address amplifier block 106 to latch the address is also generated by the RAS main signal generation circuit 104.
In the address amplifier block 106, the address signal is latched using the latch signal generated by the RAS main signal generation circuit 104 and amplified. An amplified internal address signal AD is supplied to both the pre-decode circuit 107 and the row redundant address decision circuit 109. The internal address signal AD supplied to the row redundant address decision circuit 109 is further send to the redundant word decoder 110 as a redundant address signal RA. The internal address signal AD supplied to the pre-decode circuit 107 is pre-decoded, and then, a pre-decoded internal address signal is sent to the primary word decoder 108.
Next, the row redundant address decision circuit 109 decides whether the supplied internal address AD corresponds to the row address which selects the word line of a memory word that includes a defective memory cell and sends a result of the decision to the word decoder trigger signal generation circuit 111. The word decoder trigger signal generation circuit 111 selects either the redundant word decoder 110 or the primary word decoder 108. If the result of the selection is, for example, HIGH, then the redundant word decoder 110 is selected through a trigger signal TR1 and the redundant word line RWL is activated. As a result, the memory cell in the redundant memory cell array 113 is selected and data 123 is written to or read from the redundant memory cell through the input/output circuit 115. On the other hand, if the result of the selection is, for example, LOW, then the primary word decoder 108 is selected through a trigger signal TR2 and the primary word line WL is activated. As a result, the memory cell in the primary memory cell array 112 is selected and the data 123 is written to or read from the primary memory cell through the input/output circuit 115.
FIG. 3 shows an example of an address amplifier for one address line. The address amplifier mainly has inverters 301, 303, 304, 305 and 306 and a switch 302. When a latch signal 311 is HIGH, the switch 302 has a conduction (ON) state. Therefore, an input address signal 310 is output from the switch 302. When the input address signal 310 is HIGH, the HIGH level signal is output from the switch 302 and an output of the inverter 303 becomes LOW. Then, an output of the inverter 304 becomes HIGH. As a result, the LOW level is held at the output of the inverter 303 after the latch signal 311 becomes LOW and the switch 302 becomes off-state. An internal address signal 312 is output from the inverter 306 through the inverters 305.
FIG. 4 shows a connection between the address amplifier and the row redundant address decision circuits according to the prior art. Especially, FIG. 4 shows the connection between the output of one address amplifier 300 and the inputs of the row redundant address decision circuits 401 to 404 for one input address line. As shown in FIG. 4, the output of the address amplifier 300 is connected to all the inputs of the row redundant address decision circuits 401 to 404.
FIG. 5 shows the connection between the address amplifier 300 and the row redundant address decision circuits 401 and 403 as shown in FIG. 4. In the row redundant address decision circuit group 109 as shown in FIG. 4, there exists one row redundant address decision circuit B 403 corresponding to a row redundant address decision circuit A 401 having an inverter 501 at its input. This is because there are two cases, as follows. One case is that the input address becomes a redundant address when the output of the address amplifier 300 is HIGH. Another case is that the input address becomes the redundant address when the output of the address amplifier 300 is LOW. Therefore, the row redundant address decision circuit B 403 consists of the row redundant address decision circuit A 401 and the inverter 501 connected to the input of the row redundant address decision circuit A 401.
However, in the prior art described above, there is a disadvantage that the address amplifier is overloaded because the output of the address amplifier is connected to all the row redundant address decision circuits. This results in a slow operation speed of the semiconductor memory device.